DESIGN AND CHARACTERIZATION OF LOW-POWER LOW-NOISE ALLDIGITAL SERIAL LINK FOR POINT-TO-POINT COMMUNICATION IN SOC

The fully-digital implementation of serial links has recently emerged as a viable
alternative to their classical analogue counterpart. Indeed, reducing the analogue
content in favour of expanding the digital content becomes more attractive due to the
ability to achieve less power consumption, less sensitivity to the noise and better
scalability across multiple technologies and platforms with inconsiderable
modifications. In addition, describing the circuit in hardware description languages
gives it a high flexibility to program all design parameters in a very short time
compared with the analogue designs which need to be re-designed at transistor level
for any parameter change. This can radically reduce cost and time-to-market by
saving a significant amount of development time. However, beside these considerable
advantages, the fully-digital architecture poses several design challenges.