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Studies on Core-Based Testing of System-on-Chips Using Functional Bus and Network-on-Chip Interconnects

Hussin, Fawnizu Azmadi (2008) Studies on Core-Based Testing of System-on-Chips Using Functional Bus and Network-on-Chip Interconnects. PhD thesis, Nara Institute of Science and Technology.

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Abstract

The tests of a complex system such as a microprocessor-based system-onchip (SoC) or a network-on-chip (NoC) are difficult and expensive. In this thesis, we propose three core-based test methods that reuse the existing functional interconnects-a flat bus, hierarchical buses of multiprocessor SoC's (MPSoC), and a N oC-in order to avoid the silicon area cost of a dedicated test access mechanism (TAM). However, the use of functional interconnects as functional TAM's introduces several new problems. During tests, the interconnects-including the bus arbitrator, the bus bridges, and the NoC routers-operate in the functional mode to transport the test stimuli and responses, while the core under tests (CUT) operate in the test mode. Second, the test data is transported to the CUT through the functional bus, and not directly to the test port. Therefore, special core test wrappers that can provide the necessary control signals required by the different functional interconnect are proposed. We developed two types of wrappers, one buffer-based wrapper for the bus-based systems and another pair of complementary wrappers for the NoCbased systems. Using the core test wrappers, we propose test scheduling schemes for the three functionally different types of interconnects. The test scheduling scheme for a flat bus is developed based on an efficient packet scheduling scheme that minimizes both the buffer sizes and the test time under a power constraint. The schedulingscheme is then extended to take advantage of the hierarchical bus architecture of the MPSoC systems. The third test scheduling scheme based on the bandwidth sharing is developed specifically for the NoC-based systems. The test scheduling is performed under the objective of co-optimizing the wrapper area cost and the resulting test application time using the two complementary NoC wrappers. For each of the proposed methodology for the three types of SoC architec .. ture, we conducted a thorough experimental evaluation in order to verify their effectiveness compared to other methods.

Item Type: Thesis (PhD)
Academic Subject : Academic Department - Information Communication Technology
Subject: T Technology > T Technology (General)
Divisions: Sciences and Information Technology
Depositing User: Users 2053 not found.
Date Deposited: 30 Sep 2013 16:55
Last Modified: 25 Jan 2017 09:44
URI: http://utpedia.utp.edu.my/id/eprint/7479

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