OPTIMIZATION OF TWO FISH ENCRYPTION ALGORITHM ON FPGA

The demand for efficient and secure ciphers has given rise to a new generation of block ciphers
capable of providing increased protection at lower cost. Among these new algorithms is Twofish.
Twofish is a promising 128-bit block which was one of the 5 finalists in the National Institute of
Standards and Technology organized competition as the Advanced Encryption Standard. The aim
of the competition was to find a suitable candidate to replace DES at the core of many encryption
systems worldwide.
Twofish can work with variable key lengths: 128, 192 or 256 bits. In this report, only a version of
128-bit key length was discussed. Twofish has 6 main building blocks; Feistel Networks,
whitening, S-boxes, MDS Matrices, Pseudo Hadamard Transforms and Key Schedule. Twofish is
a 16 round Feistel network with a bijective F function, which corresponds to 8 cycles. The
whitening technique employed substantially increases the difficulty of keysearch attacks against
the remainder of the cipher. Twofish uses 4 different, bijective, key-dependent, 8-by-8 bit Sboxes.
Twofish uses a single 4 by 4 MDS matrix over GF (28).This is one of the 2 main diffusion
elements of Two fish. There is also Reed-Solomon code with the MDS property used in the key
schedule; this doesn't add diffusion to the cipher but does add diffusion to the key schedule.)
Besides that, Twofish also uses a 32 bit Pseudo Hadamard Transform to mix the outputs from its
2 parallel 32-bit g functions. Finally, Twofish needs a lot of key material, and has complicated
key schedule. To facilitate analysis, the key schedule uses the same primitives as the round
function. Except for 2 additional rotations, each pair of expanded key words is constructed by
applying the Twofish round function (with key-dependent).
For this project, 2 different optimized designs were implemented. The first design
(Design I) was implemented with minimum hardware resources usage, using a single F -Function
(modified) and was optimized with reasonable latency, throughput and throughput per gate. As
for the second design (Design 2) was implemented with reasonably minimum hardware resources
using 4 units of F-Function(modified) of Design I, minimum hardware resources usage, very
small latency, very high throughput and very high throughput per gate. Furthermore, both Design
I and Design 2 were implemented with zero keying and function as encryptor/decryptor. Both
Design I and Design 2 were written using VHDL, simulated using ALDEC, synthesized using
XILINX Synthesizing Tools, implemented using XILINX ISE6.2i implementation tools and
download onto the Spartan 2 FPGA board using BEDLOAD utility program.
As a conclusion this Final Year Project is quite successful because all the objectives have
been met successfully