Welcome To UTPedia

We would like to introduce you, the new knowledge repository product called UTPedia. The UTP Electronic and Digital Intellectual Asset. It stores digitized version of thesis, final year project reports and past year examination questions.

Browse content of UTPedia using Year, Subject, Department and Author and Search for required document using Searching facilities included in UTPedia. UTPedia with full text are accessible for all registered users, whereas only the physical information and metadata can be retrieved by public users. UTPedia collaborating and connecting peoples with university’s intellectual works from anywhere.

Disclaimer - Universiti Teknologi PETRONAS shall not be liable for any loss or damage caused by the usage of any information obtained from this web site.Best viewed using Mozilla Firefox 3 or IE 7 with resolution 1024 x 768.

Design Common Mode Logic(CML) Frequency Divider in CMOS Porcess Technology

Mastura Binti Omar, Mastura (2009) Design Common Mode Logic(CML) Frequency Divider in CMOS Porcess Technology. Universiti Teknologi Petronas, Seri Iskandar ,Tronon,Perak. (Unpublished)

Full text not available from this repository.


The objective of this project is to design current mode logic (CML) frequency divider in CMOS technology. The current spikes that occur during transition between tacking and latch mode in transistor will degrade the performance of the frequency divider. The parasitic capacitances that exist in two transistor of tracking circuit directly contribute to the latch delay. The fundamental of this project is to understand the basic operation of CML of D Flip-flop based frequency divider. The new circuit which known as modified frequency divider is designed in order to overcome the current spike that occur during the transition between track and latch mode hence to reduce the rise time and fall time at the output. The modified frequency divider is able to reduce 20% up until 57.14% of the current spike that occurs during the transition between the track and latch mode. It also managed to reduce 11.76% up until 53.85% of the rise time and fall time at the output voltage hence reduce the latch delay.

Item Type: Final Year Project
Subject: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Sciences and Information Technology
Depositing User: Users 5 not found.
Date Deposited: 11 Jan 2012 12:24
Last Modified: 19 Jan 2017 15:48
URI: http://utpedia.utp.edu.my/id/eprint/1048

Actions (login required)

View Item View Item