Design Common Mode Logic(CML) Frequency Divider in CMOS Porcess Technology

The objective of this project is to design current mode logic (CML) frequency
divider in CMOS technology. The current spikes that occur during transition
between tacking and latch mode in transistor will degrade the performance of the
frequency divider. The parasitic capacitances that exist in two transistor of
tracking circuit directly contribute to the latch delay. The fundamental of this
project is to understand the basic operation of CML of D Flip-flop based
frequency divider. The new circuit which known as modified frequency divider is
designed in order to overcome the current spike that occur during the transition
between track and latch mode hence to reduce the rise time and fall time at the
output. The modified frequency divider is able to reduce 20% up until 57.14% of
the current spike that occurs during the transition between the track and latch
mode. It also managed to reduce 11.76% up until 53.85% of the rise time and fall
time at the output voltage hence reduce the latch delay.