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Acceleration of the Presenter Detection Algorithms Using FPGA as a Coprocessor for Effective Video Recording

Xiang, Gan Yong (2015) Acceleration of the Presenter Detection Algorithms Using FPGA as a Coprocessor for Effective Video Recording. IRC, Universiti Teknologi PETRONAS. (Unpublished)

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In a video recording of a presentation session, presenter detection is required in order for the camera to have the ability to track the face of the presenter. High computation power is required to perform video processing for the detection of the presenter. Instead of using a normal embedded to perform real time video processing, Field Programmable Gate Array (FPGA) can be used as a coprocessor to perform complex computation algorithm. FGPA coprocessors can be used with standard microprocessor or microcontroller to handle complex tasks and subsequently improve the performance.

Item Type: Final Year Project
Academic Subject : Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - Design
Subject: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Engineering > Electrical and Electronic
Depositing User: Ahmad Suhairi Mohamed Lazim
Date Deposited: 28 Sep 2015 10:22
Last Modified: 25 Jan 2017 09:36
URI: http://utpedia.utp.edu.my/id/eprint/15576

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