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DESIGN-FOR-TESTABILITY (DFT) TECHNIQUE FOR OPEN FAULTS IN CMOS LATCH/FLIP-FLOP

MOHAMMAD, MARLIANA (2008) DESIGN-FOR-TESTABILITY (DFT) TECHNIQUE FOR OPEN FAULTS IN CMOS LATCH/FLIP-FLOP. Universiti Teknologi Petronas. (Unpublished)

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Abstract

In this report, CMOS 0-latch with and without open faults are designed. Schematics and layout are simulated using Cadence Spectre. The process parameter used in design is Technology AMJ06. The results obtained from the simulation are observed for both cases (with open and without open fault). It is proven that there are certain open locations in CMOS 0-latch could not be detected instantly. This is where the purpose of designing the OFT comes in. OFT circuitry is added to the 0-Jatch to create voltage competition in the circuit. With OFT circuitry implemented in the 0- latch, the open fault can be detected easily. From observation, the output at the memory state is flipped during testing. The layout for 0-latch with added OFT circuitry is also included.

Item Type: Final Year Project
Academic Subject : Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - Test and Reliablity
Subject: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Engineering > Electrical and Electronic
Depositing User: Users 2053 not found.
Date Deposited: 30 Sep 2013 16:20
Last Modified: 25 Jan 2017 09:45
URI: http://utpedia.utp.edu.my/id/eprint/7139

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