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Parallel Pipeline Implementation of 64-bit FPU on Hardware

Ng , Kiat Hong (2004) Parallel Pipeline Implementation of 64-bit FPU on Hardware. Universiti Teknologi Petronas. (Unpublished)

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Abstract

This project is entitled "Parallel Pipelined Implementation of 64-bit FPU on Hardware". Most modern processors typically have two different logic units which handlethe calculations requiredby the computer. One of them is the arithmetic-logic unit (ALU) which operates on integer operands while the other is the floating point unit (FPU) which operates on real operands. The aim of this project is therefore to create a FPUwhich complies withthe IEEE-754 double precision standard (64-bit). The project also aims to study the speed improvements offered by parallel and pipelined design. The project also requires application of advanced digital design techniques by using Verilog in a real world project. The designed FPU is targeted to be capable of performing floating point addition (FADD), subtraction (FSUB), multiplication (FMUL) and division (FDIV) operations equally as fast. The FPU must also demonstrate the performance rewards of the parallel and pipeline design. It is thus implied that the project would require an initial study on FP numbers and FP arithmetic. How FP arithmetic is actually implemented in hardware must also be know in-depth. The section on methodology details each steps that is expected to be taken throughout the course of the project. The methodology would serve as a general guideline to execute the project and more details and other refinements may be made as further progress is made into the project. The project basically has two main phases, the first being software RTL coding to be completed in semester 1 while the second is hardware implementation and testing in FPGA. The results available from the project thus far is incomplete, because of time constraints, the Verilog coding is not totally finished. Oncethe codes are done, RTL tests and simulation would need to be conducted, and then only will it be implemented on the FPGA.

Item Type: Final Year Project
Academic Subject : Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - Computer Systems Architecture
Subject: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Engineering > Electrical and Electronic
Depositing User: Users 2053 not found.
Date Deposited: 30 Sep 2013 16:55
Last Modified: 25 Jan 2017 09:47
URI: http://utpedia.utp.edu.my/id/eprint/7543

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