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THE IMPACT OF LOW DUTY CYCLES IN HIGH FREQUENCY GATE DRIVER

AB. RAHIM, ATIQAH (2011) THE IMPACT OF LOW DUTY CYCLES IN HIGH FREQUENCY GATE DRIVER. Universiti Teknologi Petronas. (Unpublished)

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Abstract

This study is about the impact of low duty cycle in high frequency gate driver. Duty cycle is important for power electronic device to make it work efficiently. Thus, the objective for this project is to design the lowest duty cycle as possible in order to observe the impact on gate driver and converter. The different value of duty cycle will be applied to two different types of gate drivers which are conventional gate driver and resonant gate driver. By applying pulse width modulation (PWM) to gate driver switches, it will be determined the duty cycle of the gate driver. The PWM is fed directly to both switches on drive circuit to activate the power MOSFET. Thus, by changing the PWM value, it will affect the duty cycle of the gate driver and resultant power MOSFET, M3. Therefore, the different output voltage, output current and operation mode of buck converter can be determined from the duty cycle at M3. Thus, the lowest duty cycle can be obtained with respect to the buck converter's performance. Some basic calculations and relationship between duty ratios to the converter will be explored in this work. However, the dead time application needs to be considered to avoid cross conduction for gate driver circuit to improve the efficiency of the driver. The findings show the lowest duty cycle of high frequency CGD is 16 % whilst 15 % forRGD.

Item Type: Final Year Project
Academic Subject : Academic Department - Electrical And Electronics - Communications - Microwaves and Radio Frequency - Active Devices - HBT
Subject: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Engineering > Electrical and Electronic
Depositing User: Users 2053 not found.
Date Deposited: 09 Oct 2013 11:07
Last Modified: 25 Jan 2017 09:42
URI: http://utpedia.utp.edu.my/id/eprint/8746

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