Improvised Reliability Tool for Fault Tolerance Computation

As a size of CMOS transistors in electronic circuits reduced, certainly, the reliability of circuit will decrease as well. Therefore, during designing stage measuring reliability becomes important subject as it will save time and cost of manufacturing. In current literature several reliability models are available. From these models Probabilistic Transfer Matrix (PTM) model gives results more quicker and more accurate compare to others. But these tools measures circuit reliability on manual basis. This project aims to generalize PTM model by creating a tool using Matlab programming language that will measure reliability on Auto-basis. For circuits reliability computation user need to provide netlist of circuit in the form of Gate Sequence Matrix (GSM), Circuit Specification Matrix (CSM) and Gate Location Matrix (GLM). Number of inputs, number of outputs, types of logic gates, their interconnection and layout of logic gates in the circuit described in the netlist of circuit. Reliability tool measures circuit performance in a short period of time compare to conventional manual calculations. Several benchmark test circuits such as C17, Full Adder and 2-4 Decoder simulated in order to calculate reliability of the circuit.