Design Common Mode Logic (CML) Frequency Divider In CMOS Process Technology

The objective of this project is to design current mode logic (CML) frequency divider in CMOS technology. The current spikes that occur during transition between tacking and latch mode in transistor will degrade the performance of the frequency divider. The parasitic capacitances that exist in two transistor of tracking circuit directly contribute to the latch delay. The fundamental of this
project is to understand the basic operation of CML of D Flip-flop based frequency divider.