IMPACT OF SCALING TRENDS IN CMOS DEVICES

As the development of a technology, semiconductor needs to be smaller and more advance. According to Moore’s law, the scaling of MOSFETs, which are the key segments in computerized innovation, has changed the semiconductor business and has likewise, empowered the acknowledgment of the hugely unpredictable device and frameworks that individuals depend on at present. Unfortunately, as the device scale down, a lot of implication occur such as sub threshold leakage, interconnect delay and gate level radiation hardening. Radiation is one of the most severe problem in CMOS scaling as it will lead to single event effect that consist of soft error and hard error . This project focuses on soft error reduction as itirequiresilessicharge depositionito alterithe valueistored in the amplifier circuit. Softierrors areimainly classifiediinto two types: which are single event transients (SETs) or SEUs.In this work, amplifier are used as a targeted circuit to observe the endurance of the circuit in the radiation hardened and the scaling factor. To reduce the impact of radiation in amplifier this project need to be complete to improve amplifier performance. As the features size of integrated circuit goes down to the nanometer scale,transient and permanent reliability issues are becoming a significant concern foricircuit designers. Traditionally, the reliability issues were mostly handled at the device level as a device engineering problem. However, the increasing severityiof reliability ichallenges and higher error rates due to transient upsets favor higher-level design for reliability. In this work, amplifier circuit will be developed at the circuit level. A major source ofi transient errors is the single event upset (SEU). This study does more research and the result will only base in simulation process. The simulation tool used is Cadence Virtuoso.