PROBABILISTIC METHODS FOR NANG-COMPUTING

As CMOS transistors enter below 20nm dimension, the frequent static and
intermiitent dynamic fluctuation will result to variations in the electrical parameters of
those transistors. In tum, these variations will cause the performance of CMOS
transistors to be unstable, which will then continue to develop a negative impact on
the correct functioning and reliability of those transistors. As a result, designing a
reliable circuit system based on these transistors is becoming very challenging. Thus,
we are inevitably faced with the question of how to build a reliable computing system
using nano-based CMOS transistors. Even though researchers and engineers have
developed various methodologies, which able to tolerate extremely large number of
defects and faults by CMOS transistors, the question of quantifying reliability of the
computing system at design stage still remains the same.