ANWER, JAHANZEB ANWER (2011) ENHANCEMENT OF MARKOV RANDOM FIELD MECHANISM TO ACHIEVE FAULT-TOLERANCE IN NANOSCALE CIRCUIT DESIGN. Masters thesis, UNIVERSITI TEKNOLOGI PETRONAS.
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Abstract
As the MOSFET dimensions scale down towards nanoscale level, the reliability of
circuits based on these devices decreases. Hence, designing reliable systems using
these nano-devices is becoming challenging. Therefore, a mechanism has to be
devised that can make the nanoscale systems perform reliably using unreliable circuit
components. The solution is fault-tolerant circuit design. Markov Random Field
(MRF) is an effective approach that achieves fault-tolerance in integrated circuit
design. The previous research on this technique suffers from limitations at the design,
simulation and implementation levels. As improvements, the MRF fault-tolerance
rules have been validated for a practical circuit example. The simulation framework is
extended from thermal to a combination of thermal and random telegraph signal
(RTS) noise sources to provide a more rigorous noise environment for the simulation
of circuits build on nanoscale technologies. Moreover, an architecture-level
improvement has been proposed in the design of previous MRF gates. The redesigned
MRF is termed as Improved-MRF.
The CMOS, MRF and Improved-MRF designs were simulated under application
of highly noisy inputs. On the basis of simulations conducted for several test circuits,
it is found that Improved-MRF circuits are 400 whereas MRF circuits are only 10
times more noise-tolerant than the CMOS alternatives. The number of transistors, on
the other hand increased from a factor of 9 to 15 from MRF to Improved-MRF
respectively (as compared to the CMOS). Therefore, in order to provide a trade-off
between reliability and the area overhead required for obtaining a fault-tolerant
circuit, a novel parameter called as ‘Reliable Area Index’ (RAI) is introduced in this
research work. The value of RAI exceeds around 1.3 and 40 times for MRF and
Improved-MRF respectively as compared to CMOS design which makes Improved-
MRF to be still 30 times more efficient circuit design than MRF in terms of
maintaining a suitable trade-off between reliability and area-consumption of the
circuit.
Item Type: | Thesis (Masters) |
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Departments / MOR / COE: | Engineering > Electrical and Electronic |
Depositing User: | Users 6 not found. |
Date Deposited: | 05 Jun 2012 08:17 |
Last Modified: | 25 Jan 2017 09:42 |
URI: | http://utpedia.utp.edu.my/id/eprint/2862 |