STUDY OF HIGH FREQUENCY RESONANT GATE DRIVER FOR ZERO VOLTAGE SWITCHED SYNCHRONOUS RECTIFIER BUCK CONVERTER (ZVS-SRBC) CIRCUIT

In this work, a new Synchronous Rectifier Buck Converter (SRBC) circuit is proposed that reduces low switching and conduction losses. Moreover, the Miller effect has also been reduced. The limitations of existing single-channel resonant gate driver (S-CRGD) is studied to determine the optimized parameter values in terms of duty cycle, dead time and resonant inductance. The findings result in designing the new SRBC circuit’s symmetrical dual-channel resonant gate drive (D-CRGD). The aim is to generate low switching and gate drive losses by operating in Zero Voltage Switching (ZVS) and lower on-state drain voltage conditions. It is found that the SRBC can operate effectively at 1 MHz compared to the conventional SRBC in solving the issues of dead time and effect of switching frequency. Experimental results are presented to validate the analysis of the proposed design procedure and to demonstrate the performance of the proposed approach. In addition, several gate drive control schemes such as Fixed Dead Time (FDT), Adaptive Gate Drive (AGD) and Predictive Gate Drive (PGD) have been simulated and the results show that FDT can operate SRBC correctly with shorter dead time and eventually reduce body diode conduction loss. Even though FDT is prone to cross-conduction effect, the design stage is simple. Apart from this, AGD and PGD control schemes have also shown high level of efficiency. However, AGD generates more losses which makes PGD preferable in achieving a highly efficient converter although there are advantages in FDT scheme.