A STUDY OF MRF CMOS CIRCUIT DESIGN IMPLEMENTATION

Shrinking devices to the smaller scale and reducing of voltage levels down to the
thermal limit, all conspire to produce faulty systems. One possible solution for this
matter is to have a paradigm shift to a fault tolerant probabilistic framework.
Probabilistic computing provides a new approach towards building fault-tolerant
architectures and systems. The logic states are considered to be random variables.
Under this framework, one no longer expects a correct logic signal at all nodes at all
times, but only that the joint probability distribution of signal values has the highest
likelihood for valid logic states. The probabilistic approach is based on the theory of
Markov Random Fields (MRF), which is extensible to a large number of logic
variables. This theory can be used to design the circuit with high noise immunity.
This report discusses about the inverter circuits, and comparison between the
obtained results for both MRF and Standard inverters using Cadence tools and
MA TLAB in both noisy and ideal conditions. The results are in micro-regime, since
the minimum dimensions of the software were in micro-ranges.
The project focused more on the analysis of noise for both inverters and the
transistors inside each one of them. As a result of completing the above procedure, it
was proved that MRF inverter is tolerant to noisy conditions where as the standard
inverter is not.