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'Bit-level non-destructive arbitration ofCAN controllers'

Kwong, Lai Yeen (2004) 'Bit-level non-destructive arbitration ofCAN controllers'. Universiti Teknologi Petronas. (Unpublished)

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Abstract

This report is written as part of the requirement of Final Year Project in progress. The title; "Bit-level non-destructive arbitration of CAN controllers" was selected by the author from a selection of titles provided by lecturers and approved by the Final Year Project (FYP) committee. Chapter 1 of the report presented a brief overview on the project scope and concepts applied. 11 gave some i ntroduction and a b rief history on Controller Area Network (CAN). The problem statement which leads to the implementation of the project has also been highlighted. The objective of the project has also been defined in this section in which the main aim of this project is have an FPGA implementation of a CAN controller which will be able to demonstrate the non-destructive arbitration operation when sending messages across the bus. Chapter 2 of the report discussed more on CAN in general. It explained on the CAN protocol and the principle used in the network. CAN in general is divided into three layers which is the Object Layer, Physical Layer and Transfer Layer. Each layer has its corresponding tasks or functionality in data/message handling within the network. In network data transmission, CAN uses a method known as Carrier Sense, Multiple Access with Collision Detect (CSMA/CD) but with the enhanced capability of non-destructive bitwise arbitration to handle message collision to deliver maximum use of the available capacity of the bus. In Chapter 3, the methodology used in implementing the project has been identified. The methodology schedule is based on the Gantt chart (Appendix A), The FPGA design flow used to program into the design into the FPGA chip has also been presented. In Chapter 4, some discussions and findings of CAN especially in the bitlevel arbitration process of CAN has been discussed. The Register Transfer Level (RTL) simulation results and the Logic Analyzer captured output waveform has been analyzed and verified. The last section consists of the conclusion and some recommendations to improve on the design.

Item Type: Final Year Project
Academic Subject : Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - Design
Subject: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Engineering > Electrical and Electronic
Depositing User: Users 2053 not found.
Date Deposited: 30 Sep 2013 16:55
Last Modified: 25 Jan 2017 09:47
URI: http://utpedia.utp.edu.my/id/eprint/7908

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