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ONG, JALEN SUET YENG (2007) 8 BIT REGISTER-BASED ALU ON FPGA. Universiti Teknologi PETRONAS. (Unpublished)

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The objective of the project is to implement the ALU of an 8 bit register-based CPU on FPGA. The success of this project will be an asset to the education of computer architectures. Exposure to FPGA design will also become invaluable as the demand for embedded system increases. The scope of study involves gaining understanding of the architecture ofthe CPU and mastering HDL for FPGA design. The methodologies outlined include functional and timing analysis of the ALU, construction of test jigs for hardware interface with UP2 development board, hardware tests and troubleshooting, programming TTL components in Verilog, construction of interface with TTL CPU, interfacing with TTL CPU and implementing the control card on FPGA. A functional ALU was implemented on FPGA. Static tests have shown that the ALU unit is functioning.

Item Type: Final Year Project
Academic Subject : Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - Design
Subject: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Engineering > Electrical and Electronic
Depositing User: Users 2053 not found.
Date Deposited: 22 Oct 2013 14:38
Last Modified: 25 Jan 2017 09:45
URI: http://utpedia.utp.edu.my/id/eprint/9470

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