DESIGNING LOW VOLTAGE AND POWER CMOS OP AMP

The importance of using low supply voltage for analogue circuit has enormously
increased in recent past. The recent trend shows that a supply voltage can be degraded
until 1.5 V. Low power consumption also important to increase the battery life, the
packaging density and circuit reliability. CMOS op amp technology today can have
power consumption lower than 200 uW. The objective of this project is to design low
supply voltage and low power consumption CMOS operational amplifier.
Low supply voltage op amp with 1.6 V has been successfully designed. The design was
using bulk-driven PMOS transistors as an input differential of the op amp. The
compensation capacitor was also used to control the power consumption. The op amp is
capable of producing low power consumption of 20 uAV. The layout was design using
0.35 urn technology and have gone through DRC and LVS check. Software Virtuoso
Schematic Capture and Virtuoso Spectre Circuit Simulator from cadence have been used
for schematic capture and design simulation. For layout design, DRC and LVS check,
softwere Calibre from Mentor Graphic have been used.
IV