DESIGNING LOW VOLTAGE AND POWER CMOS OP AMP

Yusoff, Mohd Ridzuan (2007) DESIGNING LOW VOLTAGE AND POWER CMOS OP AMP. [Final Year Project] (Unpublished)

[thumbnail of 2007 -Designing Low Voltage And Power CMOS OP AMP.pdf] PDF
2007 -Designing Low Voltage And Power CMOS OP AMP.pdf

Download (1MB)

Abstract

The importance of using low supply voltage for analogue circuit has enormously
increased in recent past. The recent trend shows that a supply voltage can be degraded
until 1.5 V. Low power consumption also important to increase the battery life, the
packaging density and circuit reliability. CMOS op amp technology today can have
power consumption lower than 200 uW. The objective of this project is to design low
supply voltage and low power consumption CMOS operational amplifier.
Low supply voltage op amp with 1.6 V has been successfully designed. The design was
using bulk-driven PMOS transistors as an input differential of the op amp. The
compensation capacitor was also used to control the power consumption. The op amp is
capable of producing low power consumption of 20 uAV. The layout was design using
0.35 urn technology and have gone through DRC and LVS check. Software Virtuoso
Schematic Capture and Virtuoso Spectre Circuit Simulator from cadence have been used
for schematic capture and design simulation. For layout design, DRC and LVS check,
softwere Calibre from Mentor Graphic have been used.
IV

Item Type: Final Year Project
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments / MOR / COE: Engineering > Electrical and Electronic
Depositing User: Users 2053 not found.
Date Deposited: 24 Oct 2013 14:46
Last Modified: 25 Jan 2017 09:45
URI: http://utpedia.utp.edu.my/id/eprint/9677

Actions (login required)

View Item
View Item