Development of Lifting-based VLSI Architectures for Two-Dimensional Discrete Wavelet Transform

Two-dimensional discrete wavelet transform (2-D DWT) has evolved as an essential
part of a modem compression system. It offers superior compression with good image
quality and overcomes disadvantage of the discrete cosine transform, which suffers
from blocks artifacts that reduces the quality of the inage. The amount of
computations involve in 2-D DWT is enormous and cannot be processed by generalpurpose
processors when real-time processing is required. Th·"efore, high speed and
low power VLSI architecture that computes 2-D DWT effectively is needed. In this
research, several VLSI architectures have been developed that meets real-time
requirements for 2-D DWT applications. This research iaitially started off by
implementing a software simulation program that decorrelates the original image and
reconstructs the original image from the decorrelated image. Then, based on the
information gained from implementing the simulation program, a new approach for
designing lifting-based VLSI architectures for 2-D forward DWT is introduced. As a
result, two high performance VLSI architectures that perform 2-D DWT for 5/3 and
9/7 filters are developed based on overlapped and nonoverlapped scan methods. Then,
the intermediate architecture is developed, which aim a·: reducing the power
consumption of the overlapped areas without using the expensive line buffer. In order
to best meet real-time applications of 2-D DWT with demanding requirements in
terms of speed and throughput parallelism is explored. The single pipelined
intermediate and overlapped architectures are extended to 2-, 3-, and 4-parallel
architectures to achieve speed factors of 2, 3, and 4, respectively. To further
demonstrate the effectiveness of the approach single and para.llel VLSI architectures
for 2-D inverse discrete wavelet transform (2-D IDWT) are developed. Furthermore,
2-D DWT memory architectures, which have been overlooked in the literature, are
also developed. Finally, to show the architectural models developed for 2-D DWT are
simple to control, the control algorithms for 4-parallel architecture based on the first
scan method is developed. To validate architectures develcped in this work five
architectures are implemented and simulated on Altera FPGA.

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