OPTIMIZATION OFADVANCEDENCRYPTION STANDARD (AES) IN FPGA IMPLEMENTATION USING S-BOX INTEGRATION

Cryptography has a significant role in the security of data transmission. The
algorithm of Rijndael was selected and adopted by National Institute of Standards
and Technology (NIST) U.S. as Advanced Encryption Standard (AES) in October
2000, in order to replace the old Data Encryption Standard (DES).
As compared to software, hardware implementations provide more physical security
as well as faster speed. Thus, in this project, the AES cryptograph was simulated
with FPGA, by using Verilog HDL. The main objectives are the architectural and
algorithmic optimizations of the AES implementation, which would in turn benefit
applications that are both speed and area critical.
The optimization methodology in this project was achieved using S-Box integration.
S-Box, which is for SubBytes, and Inverse S-Box, which is for InvSubBytes, are both
constituted of two 256-byte substitution tables. In fact, it is usual that in any high
speed full pipelining AES implementations, it would require 24 S-Box tables and 16
InverseS-Box tables at any one time.
Nonetheless, mathematical formulas show that S-Box and Inverse S-Box could
actually beachieved with only g,fand/1. Multiplicative inverse, org, is a 256-byte
look-up table. On the other hand, affine transformation,/, and its inverse,/7, can be
implemented with a limited number of XOR gates. Accordingly, the number of
substitution tables necessitated could be reduced by half.
Consequently, the new implementation would still obtain the identical S-Box and
Inverse S-Box values, but merely from one look-up table and some simple logic
gates. The new design shows that it can deliver a throughput of 203 Mbit/sec with
hardware of 78,977 gate counts. Hardware complexity is reduced to 69% of its
originalwhile still able to function at core process of only 12 cycles.