Welcome To UTPedia

We would like to introduce you, the new knowledge repository product called UTPedia. The UTP Electronic and Digital Intellectual Asset. It stores digitized version of thesis, dissertation, final year project reports and past year examination questions.

Browse content of UTPedia using Year, Subject, Department and Author and Search for required document using Searching facilities included in UTPedia. UTPedia with full text are accessible for all registered users, whereas only the physical information and metadata can be retrieved by public users. UTPedia collaborating and connecting peoples with university’s intellectual works from anywhere.

Disclaimer - Universiti Teknologi PETRONAS shall not be liable for any loss or damage caused by the usage of any information obtained from this web site.Best viewed using Mozilla Firefox 3 or IE 7 with resolution 1024 x 768.

Simple-As-Possible Computer System Development on Field Programmable Gate Array

Lee, Siang Yeek (2007) Simple-As-Possible Computer System Development on Field Programmable Gate Array. Universiti Teknologi PETRONAS. (Unpublished)

[img] PDF
Download (4Mb)

Abstract

This report presents the project work and results of the Simple-As-Possible (SAP) computer system development on Field Programmable Gate Array (FPGA) project. This project undertaken as fulfilment of the two semesters EEB5034 & EEB5044 Final Year Project course is aimed to develop the first generation of SAP computer (SAP-1) introduced by Albert Paul Malvino on FPGAs for educational purpose. This includes system level synthesis of SAP-1 computer on a single FPGA chip, as well as modular synthesis of SAP-1 with each SAP-1 functional block on a Complex Programmable Logic Device (CPLD) or FPGAchip. The objective of this project is to develop SAP-1 computer model for better structured lab practices of the Computer System Architecture course. Implementation of SAP-1 computer is initially suggested by Malvino to be based on TTL logic circuits. FPGA and CPLD are selected instead in this project due to their improved robustness and ease of debugging. The project also serves as introductory practice for understanding of fundamental computer architecture and Verilog Hardware Description Language (HDL) simulation and synthesis of digital systems to the developer.

Item Type: Final Year Project
Academic Subject : Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - Programmable Devices
Subject: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Engineering > Electrical and Electronic
Depositing User: Users 2053 not found.
Date Deposited: 24 Oct 2013 10:11
Last Modified: 25 Jan 2017 09:45
URI: http://utpedia.utp.edu.my/id/eprint/9616

Actions (login required)

View Item View Item

Document Downloads

More statistics for this item...