Simple-As-Possible Computer System Development on Field Programmable Gate Array

This report presents the project work and results of the Simple-As-Possible (SAP)
computer system development on Field Programmable Gate Array (FPGA) project.
This project undertaken as fulfilment of the two semesters EEB5034 & EEB5044
Final Year Project course is aimed to develop the first generation of SAP computer
(SAP-1) introduced by Albert Paul Malvino on FPGAs for educational purpose. This
includes system level synthesis of SAP-1 computer on a single FPGA chip, as well as
modular synthesis of SAP-1 with each SAP-1 functional block on a Complex
Programmable Logic Device (CPLD) or FPGAchip.
The objective of this project is to develop SAP-1 computer model for better
structured lab practices of the Computer System Architecture course. Implementation
of SAP-1 computer is initially suggested by Malvino to be based on TTL logic
circuits. FPGA and CPLD are selected instead in this project due to their improved
robustness and ease of debugging. The project also serves as introductory practice for
understanding of fundamental computer architecture and Verilog Hardware
Description Language (HDL) simulation and synthesis of digital systems to the
developer.